In recent years, a semiconductor chip is equipped with a timing monitor that can confirm whether data is properly propagated in a simulated manner, for the purpose of reducing power consumption of the semiconductor chip. For example, Minki Cho et al., “Post-Silicon Voltage-Guard-Band Reduction in a 22 nm Graphics Execution Cores Using Adaptive Voltage Scaling and Dynamic Power Gating”, IEEE, ISSCC (International Solid-State Circuits Conference) 2016, 2016 discloses a replica delay monitor that detects the presence or absence of a setup error by simulating a critical path in a semiconductor chip. This replica delay monitor can confirm the presence or absence of a setup error by setting a delay, in a data path between two flip-flops, the same as a delay in the critical path. By obtaining a result of determination made by the replica delay monitor while lowering power voltage of the semiconductor chip, lower power voltage can be set while maintaining the performance of the semiconductor chip.